The present invention relates to a semiconductor integrated circuit device and in particular to a technology which is effective to use for semiconductor circuit devices including a tag memory in a cache memory.
The cache memory mainly comprises a cache tag (tag memory), cache data memory and cache controller. The cache tag stores therein part of the address which is also referred to as xe2x80x9caddress tagxe2x80x9d. The cache data memory stores therein data corresponding to the address tag which is stored in the cache tag. When part of the address stored in the cache tag matches the relevant address from a central processing unit, a hit signal is generated from the cache tag, so that data read from the cache data memory which is in parallel selected is accepted to the central processing unit. If a mishit occurs, a main memory will be accessed.
Some static memory cells are used as the cache tag. The static memory cells are disposed in static memory cells in a matrix configuration. The address tag which is read from the memory cells to complementary bit lines is amplified by a sense amplifier. The amplified output is compared with the input address to generate the hit or mishit signal. A processor using the static memory cells as a cache tag is disclosed U.S. Pat. No. 5,930,523 issued to S. Kawasaki et. al. Jul. 27, 1999.
In order to perform high speed operation in the above-mentioned cache tag, it is important to obtain a result of determination whether a hit or mishit occurs as fast as possible. Accordingly, the present inventors have studied the reading of address stored in the cache tag in one memory cycle, input of corresponding address from the central processing unit and its comparing operation.
It is an object of the present invention to provide a semiconductor integrated circuit device having storing and comparing circuit incorporated therein, which has achieved a high integration, low power consumption and speeding up.
It is another object of the present invention to provide a semiconductor integrated circuit device including a cache memory which has achieved high integration, low power consumption and speeding up.
The foregoing and other objects and novel features of the present invention will become more apparent from the description of the specification and annexed claims.
In an aspect of the present invention, a signal to be written is transmitted to said pairs of writing signal lines in parallel with address input operation for the selection of a word line which is connected to said memory cell, information stored in the memory cell selected in response to the selection operation of said word line is transmitted to said pair of reading signal lines via said second selecting switch circuit so that it is amplified by said sense amplifier, and the amplified output of said sense amplifier is compared with the signal to be written on said pair of writing signal lines so that the signal to be written which is transmitted to said pair of writing signal lines is written into said selected memory cell by selectively turning on said first selecting switch circuit in response to a result of said comparison.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.